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Common PCB Mistakes & Risks

A board can pass DRC and still brown out, glitch, fail EMC, or get rejected by the fab. These are the recurring mistakes β€” grouped by area, each as cause β†’ effect β†’ fix.

Catch them in review, not after the fab run

Almost everything below is cheap to fix in schematic/layout review and expensive to fix after ordering. Run the DFM checklist before every order.

1. Power & decoupling​

  • Missing / too little decoupling β†’ rail sags on current spikes β†’ random resets, flaky logic. Fix: a 100 nF cap at every IC power pin + a bulk cap (1–10 Β΅F) per supply rail.
  • Decoupling cap placed far from the pin β†’ trace inductance kills it at high frequency. Fix: same side as the IC, shortest trace, vias straight to the plane.
  • Undersized power traces / no power plane β†’ IR drop and heating. Fix: size traces to current; use planes/pours for power and ground.
  • Forgetting regulator input/output caps β†’ LDO/buck oscillation or ripple. Fix: follow the datasheet's required caps and values.
Decoupling is not optional

A missing 100 nF cap is the classic "works on the bench, glitches in the field" bug. Every IC power pin needs local decoupling, close to the pin.

2. Grounding & return paths​

  • Split / slotted ground plane under a fast signal β†’ return current detours β†’ EMI + signal integrity problems. Fix: keep a continuous reference plane under high-speed traces.
  • Long return paths β†’ ground bounce and coupled noise. Fix: keep the return directly beneath the signal; add ground stitching vias.
  • Carelessly mixing analog and digital grounds β†’ digital noise injected into sensitive analog. Fix: plan the ground partitioning and the single connection point deliberately.

3. Signal integrity​

  • Crosstalk β€” traces packed too close or long parallel runs couple into each other β†’ noise, glitches. Fix: apply the 3W rule, shorten parallel lengths, add a ground trace/plane between.
  • Stubs, impedance discontinuities, unterminated high-speed lines β†’ reflections and ringing. Fix: keep controlled impedance continuous; terminate where required.
  • No length matching on parallel buses (e.g. memory) β†’ skew β†’ data errors. Fix: length-match within the bus tolerance.
Differential pairs need real pair routing

USB, Ethernet, CAN, HDMI and similar use differential signaling. If the two nets aren't routed as a tight, length-matched pair at the correct differential impedance (e.g. 90 Ξ© USB, 100 Ξ© Ethernet), you get intermittent enumeration, CRC errors, or a link that never comes up. Fix: route them together, length-match, and set controlled impedance from the stackup.

4. Manufacturing constraints (DFM)​

Set your design rules to the fab's capability sheet before routing β€” not after.

ConstraintIf too aggressiveConservative default (verify with fab)
Trace width / spacingEtch opens or shortsβ‰₯ 6 mil (0.15 mm)
Via drill / padDrill breakout, unreliable plating β†’ opensβ‰₯ 0.3 mm drill / 0.6 mm pad
Annular ringBreakout β†’ open viaβ‰₯ 5 mil (0.13 mm)
Copper-to-edgeExposed copper, shortsβ‰₯ 0.3 mm
Silkscreen lineUnreadable textβ‰₯ 6 mil
  • Via too small β†’ fab can't drill/plate it reliably β†’ intermittent or open connections.
  • Trace too thin β†’ for current: overheats / lifts; for the process: etches open.
  • Acute angles / acid traps and copper slivers β†’ etching defects. Fix: avoid sharp acute angles; clean up slivers.
  • No solder mask between fine-pitch pads β†’ solder bridging in assembly.
  • Asymmetric pads/thermals on small passives β†’ tombstoning (part stands up) during reflow.
Match your DRC to the chosen fab

A 4 mil trace / 0.2 mm via may be fine at an advanced fab but rejected or surcharged at a budget one. Get the manufacturer's capability sheet first and configure DRC to it β€” a clean DRC against the wrong rules still fails in production.

5. Footprints & symbols​

  • Wrong footprint, pin mapping, or pin-1 orientation β†’ unsolderable or dead board.
  • Wrong pad size / pitch, mirrored connector β†’ parts don't fit or sit backwards.
  • Library part doesn't match the datasheet β†’ silent errors that survive to assembly.
Verify every footprint against the datasheet

Footprint errors are a top cause of a board respin. Check pad dimensions, pitch and pin 1 against the official datasheet β€” not just a downloaded library symbol.

6. Thermal​

  • No copper pour / thermal vias under power ICs (buck regulators, MCUs with thermal pads) β†’ overheating, shutdown. Fix: add the recommended pour and via array.
  • No thermal relief on plane connections β†’ pads act as heat sinks β†’ cold joints, hard hand-soldering.
  • Hot parts packed together β†’ heat coupling. Fix: space and orient for airflow.

7. Process & bring-up​

  • No test points / fiducials β†’ hard to debug and to assemble (no machine alignment).
  • Missing polarity marks, pin-1 dots, labels β†’ assembly mistakes.
  • Ordering before a design review β†’ expensive respin. Fix: review schematic, layout, and the Gerbers in a viewer first.
Pre-order checklist
  • DRC clean against the fab's rules
  • Every IC decoupled; regulators have datasheet caps
  • Differential pairs routed + impedance set; buses length-matched
  • Footprints checked vs datasheets
  • Test points, fiducials, polarity marks present
  • BOM verified; Gerbers viewed before sending

References​